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First Steps with the NEORV32 RISC-V Softcore for Low-Cost FPGAs
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RISC-V Controller
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By Mathias Claußen (Elektor)
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Want to experiment with RISC-V? You can do so without a hard-wired chip. Get ready to work with the NEORV32 RISC-V softcore for low-cost FPGAs.
If you want to experiment with a RISC-V microcontroller, there are now a number of processors that use this open standard instruction set architecture, such as the new ESP32-C3. But you don’t need to opt for a hard-wired chip. There are alternatives. The NEORV32 project offers a RISC-V softcore design which you build using an FPGA. The finished processor will be a little less powerful than a hard-wired one, but it will give you a great deal more flexibility so that different designs can be tested and any in-house developed peripherals can also be integrated into your hardware. Taking this route, you will also learn a lot, for example, about the inner workings of a CPU.
A Practical Application
Even those who have already spent some time playing with FPGAs will quickly encounter hurdles when it comes to configuring their own small processor design. The entire process can be quite challenging even for experienced engineers as our series on the SCCC project by Martin Oßmann [1] showed. Fortunately, you don’t need to start from scratch. You can take advantage of some (almost turnkey) solutions already developed by dedicated experts who have made there designs freely available. One such solution, which is also under an open-source license, will be used here. This article is in no way a comprehensive course on RISC-V or FPGA technology, but it should help shorten the learning curve by showing you how to build and get your first practical application up and running as quickly as possible.
6 embedded world Special 2022 www.elektormagazine.com
FPGA, Synthesis, Softcore, RISC-V, and the Compiler
Whenever you need to choose a general-purpose microcontroller for a specific application, a range of different factors can influence your decision. One of the most basic considerations is the variety of built-in peripherals the controller chip offers. All these functions are fixed in the hardware of the particular version of the chip and cannot be changed. This approach allows manufacturers to produce low-cost chips with optimized performance. Things are different if you design your own controller using an FPGA. An FPGA itself consists of a bunch of logic cells, the lookup tables (LUT), which can be flexibly interconnected via a matrix. The blocks that exist in such a LUT are shown in Figure 1. An example is a LUT-4 element with four input signals, a truth table, a flip-flop and a multiplexer at the output. The truth table can be used to form any basic logic gate such as an AND, OR, NOT or EXCLUSIVE OR. In conjunction with the matrix within the FPGA, these components can be used to create more complex structures such as memories, adders or multiplexers, which in turn can be combined to form an even more complex system such as a processor or a complete system-on-chip. The FPGA can be compared to a box of toy building blocks that you can plug together to build a castle, for example, and then break down to build a bridge or some other structure, using the same bricks over and over again. In order for the FPGA to be able to perform a specific function, it must be configured appropriately. It is, however not necessary to
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